In a digital signal processor having both level 1 instruction (L1), level 1 data (L1D) and level 2 (L2) cache memories, there is no guarantee that when the CPU requests data from the L2 cache the data will be returned in the order of the requests. This necessitates an additional step in the L1 cache to reorder the data before providing it to the CPU. This reordering has usually been done by a reorder buffer. In high performance processors the size of this buffer may grow to an unacceptable size as the allowable outstanding memory requests and packet sizes increase. The size of the reorder buffer has a direct impact on the frequency of operation of the high performance processor and also results in increased area for the core proportional to the size of the buffer.